module count_60_ben (
    input            CLK,
    input            CLR,
    input            EN,
    output reg       COUT,
    output reg [7:0] Q
);
  reg [7:0] COUNT;
  always @(posedge CLK) begin
    if (CLR == 1) begin
      COUNT <= 8'b0;
    end else if (EN == 1) begin
      if (COUNT == 8'b0100_0000) begin
        COUNT <= 8'b0;
        COUT  <= 1'b1;
      end else if (COUNT[3:0] < 4'b1001) begin
        COUNT[3:0] <= COUNT[3:0] + 1'b1;
      end else if (COUNT[7:4] < 4'b0110) begin
        COUNT[7:4] <= COUNT[7:4] + 1'b1;
        COUNT[3:0] <= 4'b0;
        COUT       <= 1'b0;
      end
    end else begin
      COUT <= 1'b0;
    end
  end
  always @(COUNT) begin
    Q <= COUNT;
  end
endmodule
